Computer Science

1. 1.

   Describe the roles of the program counter and memory address register during instruction fetch.

   [3 marks] · no calculator

   Answer explanation

   Draft walkthroughs are based on marking guidance, not independently verified derivations.

   1. Distinguish an address from instruction contents. The address register selects a memory location; the fetched bits then travel through the data path into an instruction register for decoding.

   Marking points

   • The program counter holds the address of the next instruction.
   • That address is copied to the memory address register for the read.
   • The program counter is updated to the subsequent instruction address unless control flow changes it.

   Examiner tip: Do not say the program counter stores the instruction itself.

2. 2.

   Explain why RAM and secondary storage serve different roles when running a program.

   [3 marks] · no calculator

   Answer explanation

   Draft walkthroughs are based on marking guidance, not independently verified derivations.

   1. Loading a program copies persistent contents into accessible working memory. Saving copies selected working data back to persistent storage; merely modifying RAM does not guarantee that change survives power loss.

   Marking points

   • RAM provides fast working storage for current instructions/data.
   • Ordinary RAM is volatile and loses contents when power is removed.
   • Secondary storage retains program files persistently but generally has slower access.

   Examiner tip: Volatile means power-dependent, not 'changes frequently'.

3. 3.

   A cache lookup takes 2 ns. On a miss, an additional 50 ns memory access is needed. With hit rate 0.90, calculate mean access time under this nonoverlapping model.

   [3 marks]

   Answer explanation

   Draft walkthroughs are based on marking guidance, not independently verified derivations.

   1. Every request takes the lookup time, and one in ten also requires the additional memory access time. Equivalently, average time is 2 + 0.10(50), avoiding omission of lookup time on misses.

   Marking points

   • Hit time = 2 ns; miss time = 52 ns.
   • Use 0.90 x 2 + 0.10 x 52.
   • Mean access time = 7 ns.

   Examiner tip: Read whether the miss penalty is additional or inclusive before averaging.

4. 4.

   Explain how temporal and spatial locality can make a cache effective in a loop processing consecutive array elements.

   [3 marks] · no calculator

   Answer explanation

   Draft walkthroughs are based on marking guidance, not independently verified derivations.

   1. A cache benefits when future requests resemble recent ones. Repeated instruction fetches reuse cached bytes, while a block containing one array element may also contain the next elements.

   Marking points

   • Loop instructions and reused variables exhibit temporal locality.
   • Adjacent array addresses exhibit spatial locality.
   • Retaining recent blocks and fetching nearby data reduces main-memory accesses.

   Examiner tip: Spatial locality refers to nearby addresses, not physical closeness of processors.

5. 5.

   A program spends 60% of its original time in a section sped up by a factor of 3; the rest is unchanged. Calculate overall speedup and explain the bottleneck limit.

   [4 marks]

   Answer explanation

   Draft walkthroughs are based on marking guidance, not independently verified derivations.

   1. Partition original runtime rather than averaging speed factors. Only the improved fraction is divided by three; the unchanged work sets a lower bound on total time.

   Marking points

   • Normalised new time = 0.40 + 0.60/3.
   • New time = 0.60 of the original.
   • Speedup = 1/0.60 = 1.67 approximately.
   • Even infinitely speeding that section leaves 0.40 time, limiting speedup to 2.5.

   Examiner tip: A threefold component speedup does not mean a threefold program speedup.

6. 6.

   An interrupt occurs while a user program is executing. Explain the state-saving and return requirements, and why disabling all interrupts permanently would not be a satisfactory solution to interruption overhead.

   [4 marks] · no calculator

   Answer explanation

   Draft walkthroughs are based on marking guidance, not independently verified derivations.

   1. An interrupt is controlled temporary diversion, not abandonment of the user program. State preservation makes it transparent; masking may protect short critical regions but cannot replace normal event handling indefinitely.

   Marking points

   • Save the return program counter and required processor state.
   • Transfer control to an appropriate interrupt service routine.
   • Restore state and resume at the correct point after handling.
   • Permanent disabling can prevent timely device service, timers and scheduling, harming responsiveness/correctness.

   Examiner tip: A return address alone may not preserve registers changed by the handler.

Original, unofficial practice questions from SubjectScout — not official past-paper questions.