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From Boolean requirements to circuits and stored state

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AI-assisted English content review; independent teacher approval pending.

Practice scope and review

Original, AI-authored English practice with worked guidance. Selected topics only; independent teacher review is pending. This is not a complete syllabus, official past-paper collection or predicted exam score. Check your own exam-board specification: these concepts are not certified against a particular board or exam year.

151 original questions across 21 selected topic areas. No account or payment required to practise.

Cambridge International AS & A Level Computer Science (9618), examination year 2027: AI-assisted conceptual alignment to official sources, not teacher or exam-board certification. Syllabus mapping and remaining coverage.

5 questions in this topic

Exact English revisions checked in an AI-assisted academic review; independent teacher approval is still pending.

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Original English exercises targeting selected 9618 2027-29 requirements. Conceptual alignment only; independent teacher approval, practical competence and complete teaching coverage are not established.

Subtopics in this topic (4)
  • Combinational truth tables
  • Full adders
  • Karnaugh grouping
  • SR latch state

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Question 1An alarm sounds if it is armed A and either door D or window W is open (TRUE means open). Construct its Boolean expression, describe a gate circuit with named intermediate wires, and give the truth table in input order000 through111. Then implement the same function using two-input NAND gates only; show the intermediate expressions rather than merely naming NAND.6 indicative marks
Construct, trace and explain6 indicative marksNo calculator

An alarm sounds if it is armed A and either door D or window W is open (TRUE means open). Construct its Boolean expression, describe a gate circuit with named intermediate wires, and give the truth table in input order000 through111. Then implement the same function using two-input NAND gates only; show the intermediate expressions rather than merely naming NAND.

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Worked guidance

  1. Let X=D OR W and Y=A AND X. A two-input OR feeding a two-input AND is the direct circuit. The table rows(ADW:Y) are000:0,001:0,010:0,011:0,100:0,101:1,110:1,111:1.
  2. N1=NAND(D,D)=NOT D; N2=NAND(W,W)=NOT W; N3=NAND(N1,N2)=D OR W by De Morgan. N4=NAND(A,N3)=NOT Y; Y=NAND(N4,N4). This uses five two-input NAND gates and agrees on all eight rows.
  3. Opening a sensor without arming must not sound the alarm. A OR(D AND W) fails, for example atA=0,D=1,W=1, so the parentheses and translated circuit are substantive.

Self-marking points

View marking points
  1. Expression is A AND(D OR W).
  2. OR combines D,W; AND combines its output with A.
  3. For A=0 all four outputs are0.
  4. For A=1 outputs for DW=00,01,10,11 are0,1,1,1.
  5. NAND(D,D) and NAND(W,W) form NOT D, NOT W; NAND of these forms D OR W.
  6. NAND that OR result with A then NAND the result with itself to obtain the required positive output.

Examiner tip

Indicative distinct points, not an official Cambridge mark allocation. State bounds, assumptions and intermediate states; practical teacher review remains required.

Question 2Construct a one-bit full adder using two half adders and an OR gate. Inputs are A,B,Cin; outputs S,Cout. Give intermediate equations, all eight truth-table rows, and explain why the carry output is OR of the two half-adder carries rather than XOR of all three original inputs.6 indicative marks
Construct, trace and explain6 indicative marksNo calculator

Construct a one-bit full adder using two half adders and an OR gate. Inputs are A,B,Cin; outputs S,Cout. Give intermediate equations, all eight truth-table rows, and explain why the carry output is OR of the two half-adder carries rather than XOR of all three original inputs.

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Worked guidance

  1. A half adder adds two bits without a carry input. Feed its XOR result P into the second half adder together with Cin; combine the two carry wires using OR. The formulas are S=(A XOR B) XOR Cin and Cout=(A AND B) OR((A XOR B) AND Cin).
  2. Input000..111 has integer totals0,1,1,2,1,2,2,3. The sum output is total MOD2 and the carry is total DIV2. Thus the listed output pairs are00,10,10,01,10,01,01,11, with sum written first.
  3. At111 the three-way XOR equals1, but carry also equals1. At011 XOR equals0 while carry equals1, demonstrating that parity alone is not the carry rule.

Self-marking points

View marking points
  1. First half adder gives P=A XOR B and C1=A AND B.
  2. Second gives S=P XOR Cin and C2=P AND Cin.
  3. Cout=C1 OR C2.
  4. Rows000,001,010,011 give(S,Cout)=(0,0),(1,0),(1,0),(0,1).
  5. Rows100,101,110,111 give(1,0),(0,1),(0,1),(1,1).
  6. Carry is1 when at least two inputs are1; three-way XOR is parity, the sum output, not the carry.

Examiner tip

Indicative distinct points, not an official Cambridge mark allocation. State bounds, assumptions and intermediate states; practical teacher review remains required.

Question 3A four-variable function F(A,B,C,D) is1 exactly for minterms0,2,8,10 (ABCD interpreted as a binary number with A most significant), and0 otherwise. Use K-map rows AB=00,01,11,10 and columns CD=00,01,11,10. Locate the1s, form the largest valid group with no don't-cares, derive a simplified expression and describe its circuit.6 indicative marks
Construct, trace and explain6 indicative marksNo calculator

A four-variable function F(A,B,C,D) is1 exactly for minterms0,2,8,10 (ABCD interpreted as a binary number with A most significant), and0 otherwise. Use K-map rows AB=00,01,11,10 and columns CD=00,01,11,10. Locate the1s, form the largest valid group with no don't-cares, derive a simplified expression and describe its circuit.

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Worked guidance

  1. Binary minterms are0000,0010,1000,1010. In the supplied Gray ordering these are precisely the four corner cells. Opposite edges are adjacent, so the corners form a four-cell rectangle on the wrapped map.
  2. Across the group, A takes0/1 and C takes0/1 and both disappear. B and D are always0, leaving NOT B AND NOT D. This ignores A,C only because every combination of them with B=D=0 was explicitly included.
  3. Testing1010 gives TRUE; testing1011 gives FALSE because D=1. Without any don't-cares, grouping eight cells would include a forbidden1 and be invalid.

Self-marking points

View marking points
  1. Place1 at row00/column00 and row00/column10.
  2. Also place1 at row10/column00 and row10/column10.
  3. The four corners form one group using horizontal and vertical wraparound.
  4. A and C vary while B=0 and D=0 remain fixed.
  5. F=(NOT B) AND(NOT D), implemented with two NOT gates feeding AND.
  6. The group contains exactly the four specified minterms; no zero cell is absorbed.

Examiner tip

Indicative distinct points, not an official Cambridge mark allocation. State bounds, assumptions and intermediate states; practical teacher review remains required.

Question 4Consider an active-high SR latch made from cross-coupled NOR gates, with S driving the gate whose output is Qbar and R driving the gate whose output is Q. Start with Q=0 and Qbar=1. Give next-state behavior for SR=00,10,01,11; trace00,10,00,01,00. Explain how feedback stores a bit and why11 then simultaneous release is not a reliable data-storage operation.4 indicative marks
Construct, trace and explain4 indicative marksNo calculator

Consider an active-high SR latch made from cross-coupled NOR gates, with S driving the gate whose output is Qbar and R driving the gate whose output is Q. Start with Q=0 and Qbar=1. Give next-state behavior for SR=00,10,01,11; trace00,10,00,01,00. Explain how feedback stores a bit and why11 then simultaneous release is not a reliable data-storage operation.

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Worked guidance

  1. The equations are Q=NOT(R OR Qbar) and Qbar=NOT(S OR Q). With S=R=0 either stable complementary pair can sustain itself: that dependence on the previous state distinguishes this circuit from a combinational gate.
  2. Starting reset,00 retains0. Then10 forces Qbar0 and Q1; subsequent00 retains1. Input01 forces Q0; final00 retains0. When11 is applied both NOR outputs are0. Simultaneously releasing it does not specify a deterministic stored bit, so treat11 as invalid rather than inventing a guaranteed next state.

Self-marking points

View marking points
  1. 00 holds the prior state through feedback.
  2. 10 sets Q=1,Qbar=0; 01 resets Q=0,Qbar=1.
  3. 11 forces Q=Qbar=0 and is the forbidden noncomplementary condition.
  4. Trace Q values0,1,1,0,0 and explain that simultaneous release after11 can depend on physical timing.

Examiner tip

Indicative distinct points, not an official Cambridge mark allocation. State bounds, assumptions and intermediate states; practical teacher review remains required.

Question 5Two unsigned two-bit words are A1A0 and B1B0. Construct an equality circuit using XOR, OR and NOT and write a Boolean assignment to Equal. Evaluate word pairs (00,00),(01,10),(10,10),(11,10). Explain why comparing only the most significant bit fails.4 indicative marks
Analyse4 indicative marksNo calculator

Two unsigned two-bit words are A1A0 and B1B0. Construct an equality circuit using XOR, OR and NOT and write a Boolean assignment to Equal. Evaluate word pairs (00,00),(01,10),(10,10),(11,10). Explain why comparing only the most significant bit fails.

Cambridge 2027: Direct conceptual match

Checked four traces plus exhaustive16 word pairs against numeric equality; aligned to gate construction and Boolean simplification.

AI-assisted placement. Independent teacher approval pending.

Show indicative guidance

Worked guidance

  1. D1 <- A1 XOR B1
D0 <- A0 XOR B0
Equal <- NOT (D1 OR D0)
  2. An XOR is zero precisely when its corresponding bits agree. OR combines any disagreement, so NOT makes equality true only when both differences are zero.
  3. The four pairs give TRUE,FALSE,TRUE,FALSE. For 11 versus 10 the high bits match but the low bits differ, exposing the incomplete one-bit comparator.

Self-marking points

View marking points
  1. Forms differences D1=A1 XOR B1 and D0=A0 XOR B0.
  2. Uses Equal=NOT(D1 OR D0).
  3. Outputs TRUE,FALSE,TRUE,FALSE for the supplied pairs.
  4. Comparing only A1/B1 incorrectly accepts 11 versus 10.

Examiner tip

Both bit positions must agree; equal leading bits alone do not imply equal words.

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