Question 1Use the syllabus example assembly instruction meanings: LDR #n loads IX, LDX address loads ACC from memory[address+IX], AND/OR with Bn are bitwise, STO address stores ACC. Memory[100]=9, Memory[101]=182. Trace LDR #1; LDX 100; AND B00001111; OR B00100000; STO 200; END. Give IX, effective read address, intermediate ACC bytes and Memory[200]. Explain how to test bit2 (least-significant bit is bit0) without changing other bits in memory.6 indicative marks
Use the syllabus example assembly instruction meanings: LDR #n loads IX, LDX address loads ACC from memory[address+IX], AND/OR with Bn are bitwise, STO address stores ACC. Memory[100]=9, Memory[101]=182. Trace LDR #1; LDX 100; AND B00001111; OR B00100000; STO 200; END. Give IX, effective read address, intermediate ACC bytes and Memory[200]. Explain how to test bit2 (least-significant bit is bit0) without changing other bits in memory.
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Worked guidance
LDR #1 LDX 100 AND B00001111 OR B00100000 STO 200 END- The effective address is100+1=101, so the fetched byte is182. Masking with15 retains its low nibble6; OR with32 sets bit5, giving38. Memory[100] remains9 and Memory[101] remains182; only Memory[200] is written.
- For the stored byte38, AND4 gives4 so bit2 is1. AND8 would give0 so bit3 is0. A test can alter ACC while leaving backing memory unchanged; an AND mask is not automatically a persistent device update.
Self-marking points
View marking points
- IX becomes1 and indexed address is101.
- LDX reads182=10110110 into ACC, not address101 itself.
- AND00001111 gives00000110=6.
- OR00100000 gives00100110=38.
- STO writes38 to Memory[200].
- Load the value and AND00000100; nonzero means bit2 is set, without storing the masked result back.
Examiner tip
Indicative distinct points, not an official Cambridge mark allocation. State bounds, assumptions and intermediate states; practical teacher review remains required.